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TC6216M - 1 - ver. 2.1 5/24/01 TC6216M 16 port 10/100 unmanaged qos ethernet switch 4fl no. 106 hsin-tai wu road, sec. 1, hsichih, taipei hsien, taiwan r.o.c. tel: 886-2-2696-1669 fax: 886-2-2696-2220 http://www.tmi.com.tw/
TC6216M - 2 - ver. 2.1 5/24/01 table of contents 1 features ..................................................................................................................... .................... 3 2 description .................................................................................................................. .................. 3 3 block diagram ................................................................................................................ .............. 4 4 pin plcement ................................................................................................................. ................ 5 5 pin listing (pqfp 208)....................................................................................................... .......... 6 6 pin description.............................................................................................................. ................ 8 7 ethernet media access controller ............................................................................................. . 12 7.1 r eceive m ac ...................................................................................................................... 12 7.2 t ransmit m ac ................................................................................................................... 12 8 traffic priority ............................................................................................................. ............... 13 9 trunk configuration .......................................................................................................... ......... 14 10 flow control............................................................................................................. ................. 15 11 broadcast ................................................................................................................ ................... 15 12 auto negotiation ......................................................................................................... .............. 16 13 eeprom interface......................................................................................................... ........... 16 14 programming the eeprom for configuration....................................................................... 16 15 eeprom address map....................................................................................................... ...... 17 16 register description ..................................................................................................... ............. 18 17 timing requirements ...................................................................................................... .......... 23 18 electrical specifications ................................................................................................ ............ 26 19 mechanical specifications ................................................................................................ ......... 27 notice......................................................................................................................... ........................ 28
TC6216M - 3 - ver. 2.1 5/24/01 16 port 10/100 unmanaged qos ethernet switch 1 features !" stand alone switch on a chip !" 16 ethernet 10/100 ports with rmii interface !" port 16 is an rmii / mii port !" embedded 512kbytes ssram packet buffer !" 16k mac address table !" multiple TC6216M can produce larger switches by trunking !" 10/100 selectable for each port !" full / half duplex for each port !" highly integrated switching logic, including the mac functions on a single asic !" flow-control for full and half duplex !" three qos levels checked via ip header and 802.1q vlan tag and/or selected per port basis !" maximum throughput !" broadcast throttling !" serial eeprom interface !" mdio master for phy configuration / polling !" 3.3v/1.8v dual voltage power !" 0.6 watt power consumption !" 0.18 micron technology !" packaged in pqfp 208 2 description TC6216M is a stand-alone 16 ports 10/100 unmanaged switch controller designed for low cost high performance solutions. in addition to the basic functions of unmanaged switches it provides features usually associated with managed switches, at very high performance levels. TC6216M offers full wire-speed switching on all 16 ports, self-learning of up to 16k mac addresses, highly optimized flow control for full and half duplex, evolved traffic priority services, flexible trunking capabilities. a store-and-forward switching method using a non-blocking architecture is implemented within TC6216M to improve the availability and bandwidth. the chip embeds a 512 kbytes ssram packet buffer so the only external components required are the physical layer transceivers. normal, high and very high priority queues are implemented for each transmission port. the chip contains ieee 802.3 mac functions for 16 ports supporting both 10 mbit/s and 100 mbit/s data rates. all ports are full and half duplex capable. each port has its dedicated receive and transmit fifo?s with necessary logic to implement flow-control for both duplex modes. TC6216M utilizes pause frames as defined in ieee 802.3x for full duplex flow control, and executes backpressure for half duplex mode. no packet will be lost when flow control is operational. TC6216M provides leading edge qos with three levels of priority. the priority can be checked via layer 2 (802.1q vlan tagging) and/or layer 3 (ip header tos bits). port based priority is also provided to enable user selectable traffic prioritization. port based priority ensures transmission with precedence for all packets incoming from selected port(s). this feature allows effective video switching in multimedia applications and improved support for voice over packet applications. the chip handles a 16k mac address-lookup table with searching, self-learning, automatic aging, at a very high speed. forwarding rules are implemented according with ieee 802.1d specifications. TC6216M also provides filtering capability for bad packets, only good crc and valid sized packets will be forwarded. larger switches can be produced using TC6216M?s trunking capabilities. two trunk groups of up to four ports each can be setup with TC6216M. several load balancing schemes are provided through pins and eeprom configuration.
TC6216M - 4 - ver. 2.1 5/24/01 an external eeprom device can be used to configure the TC6216M at power-up. compared with pin configuration interface, the eeprom extends the chip?s configuration capability with new features and provides a jumperless configuration mode using a parallel print port interface for reprogramming. TC6216M can make effective use of most of its features without using the external eeprom. TC6216M uses an mdio master entity for phy autonegotiate mode polling and link status monitoring. before extracting the autonegotiation result the chip advertises full duplex flow control ability on each port and restarts the autonegotiation. effective broadcast throttling based on both broadcast buffer memory utilization and broadcast bandwidth can be performed by TC6216M. TC6216M achieves full performance at 50 mhz clock frequency. it is packaged in 208 pqfp. 3 block diagram from rx mac

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TC6216M - 5 - ver. 2.1 5/24/01 4 pin plcement sda scl miimode vss_3.3v rxclk vss_1.8v rxdat153 rxdat152 rxdat151 rxdat150 crs_dv15 crs15 col15 vdd_1.8v txclk vss_3.3v txdat153 txdat152 txdat151 txdat150 txen15 vdd_3.3v rxdat141 rxdat140 crs_dv14 vss_1.8v txdat141 txdat140 txen14 vdd_1.8v rxdat131 rxdat130 crs_dv13 vss_3.3v txdat131 txdat130 txen13 vdd_3.3v rxdat121 rxdat120 crs_dv12 vss_1.8v txdat121 txdat120 txen12 vdd_1.8v rxdat111 rxdat110 crs_dv11 vss_1.8v txdat111 txdat110 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 vss_3.3v 1 156 txen11 reset 2 155 vdd_1.8v testmode 3 154 mdclk vdd_3.3v 4 153 mdio tnka0 5 152 clk75m tnka1 6 151 clk vdd_3.3v 7 150 vdd_3.3v tnkb0 8 149 refck tnkb1 9 148 vss_1.8v vss_1.8v 10 147 rxdat101 tnkmod0 11 146 rxdat100 vss_3.3v 12 145 crs_dv10 tnkmod1 13 144 vdd_1.8v vdd_1.8v 14 143 txdat101 nc 15 142 txdat100 prtpri0 16 141 txen10 vdd_3.3v 17 140 vss_3.3v prtpri1 18 139 rxdat91 prtpri2 19 138 rxdat90 vss_1.8v 20 137 crs_dv9 prtpri3 21 136 vdd_3.3v prtpri4 22 135 txdat91 vss_3.3v 23 134 txdat90 prtpri5 24 133 txen9 prtpri6 25 132 vss_3.3v vdd_1.8v 26 131 rxdat81 prtpri7 27 130 rxdat80 prilev0 28 129 crs_dv8 vdd_3.3v 29 128 vdd_3.3v prilev1 30 127 txdat81 prilev2 31 126 txdat80 vss_1.8v 32 125 txen8 prilev3 33 124 vss_3.3v prilev4 34 123 rxdat71 vdd_1.8v 35 122 rxdat70 prilev5 36 121 crs_dv7 prilev6 37 120 vdd_1.8v prilev7 38 119 txdat71 vss_3.3v 39 118 txdat70 vdd_3.3v 40 117 txen7 enippr 41 116 vss_1.8v envlpr 42 115 rxdat61 vss_1.8v 43 114 rxdat60 fcbcsten 44 113 crs_dv6 bcstall 45 112 vdd_1.8v bcsttr 46 111 txdat61 rejmct 47 110 txdat60 vdd_1.8v 48 109 txen6 fcopt 49 108 vss_3.3v vdd_3.3v 50 107 rxdat51 disbpbk 51 106 rxdat50 vss_3.3v 52 105 crs_dv5 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 vss_1.8v disbpr fullbp vdd_1.8v powled ovbcled ovunled vss_3.3v txen0 txdat00 txdat01 vdd_3.3v crs_dv0 rxdat00 rxdat01 vss_3.3v txen1 txdat10 txdat11 vdd_1.8v crs_dv1 rxdat10 rxdat11 vss_1.8v txen2 txdat20 txdat21 vdd_1.8v crs_dv2 rxdat20 rxdat21 vss_1.8v txen3 txdat30 txdat31 vdd_1.8v crs_dv3 rxdat30 rxdat31 vss_1.8v txen4 txdat40 txdat41 vdd_3.3v crs_dv4 rxdat40 rxdat41 vss_3.3v txen5 txdat50 txdat51 vdd_3.3v TC6216M pqfp 208 top view
TC6216M - 6 - ver. 2.1 5/24/01 5 pin listing (pqfp 208) pin description pin label type pin description pin label type 1 power vss_3.3v ~ 105 rmii crs_dv5 i 2 reset reset i pu 106 rmii rxdat50 i 3 configuration testmode i pd 107 rmii rxdat51 i 4 power vdd_3.3v ~ 108 power vss_3.3v ~ 5 configuration tnka0 i pd 109 rmii txen6 o 6 configuration tnka1 i pd 110 rmii txdat60 o 7 power vdd_3.3v ~ 111 rmii txdat61 o 8 configuration tnkb0 i pd 112 power vdd_1.8v ~ 9 configuration tnkb1 i pd 113 rmii crs_dv6 i 10 power vss_1.8v ~ 114 rmii rxdat60 i 11 configuration tnkmod0 i pd 115 rmii rxdat61 i 12 power vss_3.3v ~ 116 power vss_1.8v ~ 13 configuration tnkmod1 i pd 117 rmii txen7 o 14 power vdd_1.8v ~ 118 rmii txdat70 o 15 nc nc ~ 119 rmii txdat71 o 16 configuration prtpri0 i pd 120 power vdd_1.8v ~ 17 power vdd_3.3v ~ 121 rmii crs_dv7 i 18 configuration prtpri1 i pd 122 rmii rxdat70 i 19 configuration prtpri2 i pd 123 rmii rxdat71 i 20 power vss_1.8v ~ 124 power vss_3.3v ~ 21 configuration prtpri3 i pd 125 rmii txen8 o 22 configuration prtpri4 i pd 126 rmii txdat80 o 23 power vss_3.3v ~ 127 rmii txdat81 o 24 configuration prtpri5 i pd 128 power vdd_3.3v ~ 25 configuration prtpri6 i pd 129 rmii crs_dv8 i 26 power vdd_1.8v ~ 130 rmii rxdat80 i 27 configuration prtpri7 i pd 131 rmii rxdat81 i 28 configuration prilev0 i pd 132 power vss_3.3v ~ 29 power vdd_3.3v ~ 133 rmii txen9 o 30 configuration prilev1 i pd 134 rmii txdat90 o 31 configuration prilev2 i pd 135 rmii txdat91 o 32 power vss_1.8v ~ 136 power vdd_3.3v ~ 33 configuration prilev3 i pd 137 rmii crs_dv9 i 34 configuration prilev4 i pd 138 rmii rxdat90 i 35 power vdd_1.8v ~ 139 rmii rxdat91 i 36 configuration prilev5 i pd 140 power vss_3.3v ~ 37 configuration prilev6 i pd 141 rmii txen10 o 38 configuration prilev7 i pd 142 rmii txdat100 o 39 power vss_3.3v ~ 143 rmii txdat101 o 40 power vdd_3.3v ~ 144 power vdd_1.8v ~ 41 configuration enippr i pd 145 rmii crs_dv10 i
TC6216M - 7 - ver. 2.1 5/24/01 pin description pin label type pin description pin label type 42 configuration envlpr i pd 146 rmii rxdat100 i 43 power vss_1.8v ~ 147 rmii rxdat101 i 44 configuration fcbcsten i pu 148 power vss_1.8v ~ 45 configuration bcstall i pu 149 clk refck i 46 configuration bcsttr i pd 150 power vdd_3.3v ~ 47 configuration rejmct i pu 151 clk clk i 48 power vdd_1.8v ~ 152 clk clk75m o 49 configuration fcopt i pu 153 mdio mdio i/o pu 50 power vdd_3.3v ~ 154 mdio mdclk o 51 configuration disbpbk i pd 155 power vdd_1.8v ~ 52 power vss_3.3v ~ 156 rmii txen11 o 53 power vss_1.8v ~ 157 rmii txdat110 o 54 configuration disbpr i pd 158 rmii txdat111 o 55 configuration fullbp i pd 159 power vss_1.8v ~ 56 power vdd_1.8v ~ 160 rmii crs_dv11 i 57 led powled o l 161 rmii rxdat110 i 58 led ovbcled o l 162 rmii rxdat111 i 59 led ovunled o l 163 power vdd_1.8v ~ 60 power vss_3.3v ~ 164 rmii txen12 o 61 rmii txen0 o 165 rmii txdat120 o 62 rmii txdat00 o 166 rmii txdat121 o 63 rmii txdat01 o 167 power vss_1.8v ~ 64 power vdd_3.3v ~ 168 rmii crs_dv12 i 65 rmii crs_dv0 i 169 rmii rxdat120 i 66 rmii rxdat00 i 170 rmii rxdat121 i 67 rmii rxdat01 i 171 power vdd_3.3v ~ 68 power vss_3.3v ~ 172 rmii txen13 o 69 rmii txen1 o 173 rmii txdat130 o 70 rmii txdat10 o 174 rmii txdat131 o 71 rmii txdat11 o 175 power vss_3.3v ~ 72 power vdd_1.8v ~ 176 rmii crs_dv13 i 73 rmii crs_dv1 i 177 rmii rxdat130 i 74 rmii rxdat10 i 178 rmii rxdat131 i 75 rmii rxdat11 i 179 power vdd_1.8v ~ 76 power vss_1.8v ~ 180 rmii txen14 o 77 rmii txen2 o 181 rmii txdat140 o 78 rmii txdat20 o 182 rmii txdat141 o 79 rmii txdat21 o 183 power vss_1.8v ~ 80 power vdd_1.8v ~ 184 rmii crs_dv14 i 81 rmii crs_dv2 i 185 rmii rxdat140 i 82 rmii rxdat20 i 186 rmii rxdat141 i 83 rmii rxdat21 i 187 power vdd_3.3v ~ 84 power vss_1.8v ~ 188 (r)mii txen15 o
TC6216M - 8 - ver. 2.1 5/24/01 pin description pin label type pin description pin label type 85 rmii txen3 o 189 (r)mii txdat150 o 86 rmii txdat30 o 190 (r)mii txdat151 o 87 rmii txdat31 o 191 (r)mii txdat152 o 88 power vdd_1.8v ~ 192 (r)mii txdat153 o 89 rmii crs_dv3 i 193 power vss_3.3v ~ 90 rmii rxdat30 i 194 clk txclk i 91 rmii rxdat31 i 195 power vdd_1.8v ~ 92 power vss_1.8v ~ 196 (r)mii col15 i 93 rmii txen4 o 197 (r)mii crs15 i 94 rmii txdat40 o 198 (r)mii crs_dv15 i 95 rmii txdat41 o 199 (r)mii rxdat150 i 96 power vdd_3.3v ~ 200 (r)mii rxdat151 i 97 rmii crs_dv4 i 201 (r)mii rxdat152 i 98 rmii rxdat40 i 202 (r)mii rxdat153 i 99 rmii rxdat41 i 203 power vss_1.8v ~ 100 power vss_3.3v ~ 204 clk rxclk i 101 rmii txen5 o 205 power vss_3.3v ~ 102 rmii txdat50 o 206 configuration miimode i pd 103 rmii txdat51 o 207 eeprom scl o 104 power vdd_3.3v ~ 208 eeprom sda i/o pu i ? digital input i pd ? digital input internally pulled down i pu ? digital input internally pulled up o ? digital output o l ? digital output active low i/o pu ? digital bidirectional internally pulled up 6 pin description interface signal i/o signal description reset i general reset. clk i system clock. the switch performance is full wire speed at 50mhz system clock frequency. control/clock clk75m o output clock from internal pll. for 75mhz system clock frequency tie this to system clock pin. test testmode i if set to 1 the chip will be in memory test mode. trunking tnka(0:1) tnkb(0:1) i trunking configuration. ? first trunk channel tnka1 tnka0 0 0 no port is configured as trunk port 0 1 ports 0 and 1 are configured as trunk ports 1 0 ports 0,1,2 are configured as trunk ports 1 1 ports 0,1,2 and 3 are configured as trunk ports ? second trunk channel tnkb1 tnkb0 0 0 no port is configured as trunk port 0 1 ports 15 and 14 are configured as trunk ports 1 0 ports 15, 14 , 13 are configured as trunk ports
TC6216M - 9 - ver. 2.1 5/24/01 interface signal i/o signal description 1 1 ports 15, 14 , 13 and 12 are configured as trunk ports tnkmod(0:1) i trunk balance mode select tnkmod1 tnkmod0 0 0 only source port is used to select the transmission port inside the trunk. 0 1 transmission port is selected using sa. 1 0 transmission port is selected using sa and da. 1 1 not used prtpri (0:7) i indicates which ports, if any, are in priority mode; when selected the corresponding port will have high or very high priority depending of the state of prilev pin. prtpri(0:7) are used to set the priorities for ports 4 to 11. TC6216M port (4 to 11) ! prtpri (0:7) prilev (0:7) i selects the high or very high priority for priority ports. 1 ? very high priority 0 ? high priority prilev (0:7) refers to TC6216M ports 4 to 11. enippr i enables qos resolution to consider tos precedence bits from ip header. 1 ? ip priority will be considered 0 ? ip priority will be neglected qos configuration envlpr i enables qos resolution to consider user_priority bits (tci field) from 802.1q vlan tag header. 1 ? vlan priority will be considered 0 ? vlan priority will be neglected fcbcsten i enables flow control for broadcast operation. 1 ? enable 0 ? disable bcstall i broadcast all mode select 1 ? forward broadcast packes to all the ports 0 ? forward broadcast packes to active ports only broadcast configuration bcsttr i enables broadcast throttling. 1 ? enable 0 ? disable mii mode selection miimode i select mii or rmii interface for port 15 0 ? rmii 1 ? mii mac configuration rejmct i all mac control type packets will be rejected if this pin is asserted, otherwise they will be forwarded. fcopt i flow control resolution option: 1 - the a-neg result is considered 0 ? doesn't matter the a-neg result disbpr i enable / disable flow control for half duplex mode 1 ? disable 0 ? enable flow control fullbp i when this is set to 0 then the backpressure process will be stopped after reaching 30 consecutive collisions. the default value (30) can be changed by eeprom settings. otherwise the backpressure can be executed for up to 2048 (default pause value) slot times if the flow control condition persists.
TC6216M - 10 - ver. 2.1 5/24/01 interface signal i/o signal description disbpbk i disables completely any backoff when executing backpressure: 1 ? no backoff when backpressure 0 ? aggressive backoff for backpressure power and bist powled o signals good operation state. in case of bist error the code of the error is signaled on this pin. ovbcled o signals overflow condition for broadcast operation. overflow signaling ovunled o signals overflow condition for unicast operation. sda i/o serial data. eeprom interface scl o serial clock. mdio i/o mdio bus. mdio interface mdclk o mdio clock. txdat0(0:1) o rmii tx data. txen0 o rmii tx enable. crs_dv0 i rmii carrier sense / receive data valid. rmii interface port0 rxdat0(0:1) i rmii rx data. txdat1(0:1) o rmii tx data txen1 o rmii tx enable. crs_dv1 i rmii carrier sense / receive data valid rmii interface port1 rxdat1(0:1) i rmii rx data. txdat2(0:1) o rmii tx data txen2 o rmii tx enable crs_dv2 i rmii carrier sense / receive data valid rmii interface port2 rxdat2(0:1) i rmii rx data txdat3(0:1) o rmii tx data txen3 o rmii tx enable crs_dv3 i rmii carrier sense / receive data valid rmii interface port3 rxdat3(0:1) i rmii rx data txdat4(0:1) o rmii tx data txen4 o rmii tx enable crs_dv4 i rmii carrier sense / receive data valid rmii interface port4 rxdat4(0:1) i rmii rx data txdat5(0:1) o rmii tx data txen5 o rmii tx enable crs_dv5 i rmii carrier sense / receive data valid rmii interface port5 rxdat5(0:1) i rmii rx data txdat6(0:1) o rmii tx data txen6 o rmii tx enable crs_dv6 i rmii carrier sense / receive data valid rmii interface port6 rxdat6(0:1) i rmii rx data txdat7(0:1) o rmii tx data txen7 o rmii tx enable crs_dv7 i rmii carrier sense / receive data valid rmii interface port7 rxdat7(0:1) i rmii rx data
TC6216M - 11 - ver. 2.1 5/24/01 interface signal i/o signal description txdat8(0:1) o rmii tx data txen8 o rmii tx enable crs_dv8 i rmii carrier sense / receive data valid rmii interface port8 rxdat8(0:1) i rmii rx data txdat9(0:1) o rmii tx data txen9 o rmii tx enable crs_dv9 i rmii carrier sense / receive data valid rmii interface port9 rxdat9(0:1) i rmii rx data txdat10(0:1) o rmii tx data txen10 o rmii tx enable crs_dv10 i rmii carrier sense / receive data valid rmii interface port10 rxdat10(0:1) i rmii rx data txdat11(0:1) o rmii tx data txen11 o rmii tx enable crs_dv11 i rmii carrier sense / receive data valid rmii interface port11 rxdat11(0:1) i rmii rx data txdat12(0:1) o rmii tx data txen12 o rmii tx enable crs_dv12 i rmii carrier sense / receive data valid rmii interface port12 rxdat12(0:1) i rmii rx data txdat13(0:1) o rmii tx data txen13 o rmii tx enable crs_dv13 i rmii carrier sense / receive data valid rmii interface port13 rxdat13(0:1) i rmii rx data txdat14(0:1) o rmii tx data txen14 o rmii tx enable crs_dv14 i rmii carrier sense / receive data valid rmii interface port14 rxdat14(0:1) i rmii rx data txdat15(0:3) o rmii tx data (0:1) / mii tx data (0:3) rxdat15(0:3) i rmii rx data (0:1) / mii rx data (0:3) txen15 o rmii / mii tx enable crs_dv15 i rmii carrier sense / receive data valid col15 i mii collision. txclk15 i mii tx clock. rxclk15 i mii rx clock. (r)mii interface port15 crs15 i mii carrier sense. rmii reference clock refck i rmii reference clock for port 0-15
TC6216M - 12 - ver. 2.1 5/24/01 7 ethernet media access controller the ethernet media access controller (mac) contains ieee 802.3 mac functions for 16 ports. it is able to operate in 10/100 speed modes, full and half duplex. each port has its dedicated receive and transmit fifo s with necessary logic to implement flow-control for both duplex modes. the mac functions are optimized and tailored for high speed and flexible interfacing. 7.1 receive mac when a frame is received from the ethernet media through the rmii, the data is stored in a receive fifo. the fifo acts as a temporary buffer between the receive mac section and switch core interface. the receive mac layer decomposes ethernet packets acquired from the phy layer via rmii, by stripping off the preamble sequence and sfd. the receive mac then sends packets to the receive fifo along with packet validity information. the mac determines the validity of each received packet by checking the crc and packet length. the bad packets will be dropped either by the mac or by the queue manager. oversized packets are truncated to 1536 bytes and marked to be erroneous. undersized packets are removed from the receive fifo without being reported at the switch interface. the fifo space held by undersized packets is automatically recovered by removing the packet. the receive mac is also able to reject mac control type frames (type 88-08). to activate this filtering function it must be selected using rejmct pin or the equivalent eeprom bit. when the TC6216M receives a mac control frame and determines that the opcode is a pause command (flow control frame) and the frame s crc is ok, the chip will load its internal pause counter with the time value variable extracted from the incoming flow control packet. if the pause counter is not zero the receive mac will xoff the transmit mac. the pause counter will decrement after each slot time and will xon the transmit mac when the zero value is reached. if a frame transmission is in progress when the pause frame is received, the transmission is allowed to complete but it will be stopped for the next packets until an xon command is generated by the receive mac. the pause time will begin at the end of current transmission or immediately (if no transmission is in course at the moment of receiving the pause frame). if a pause command is received while the transmitter is already in pause, the new pause time indicated by the new flow control frame will be loaded into the pause register. when the receive fifo is full and additional data are still incoming from the mac, then the overrun condition occurs and the frame is dropped. if the system clock frequency is not lower than the recommended value this condition will not occur. 7.2 transmit mac the transmit mac section assembles the mac frames stored in the transmit fifo and controls their transmission onto the media via external phy entities. it appends the standard preamble and start of frame delimiter to the transmitted packets. the transmit mac also controls the interframegap time during transmission, maintaining for default the standard minimum interframegap of 96 bit time. this value can be changed by eeprom setting. for half duplex mode the transmit mac meets csma/cd ieee 802.3 requirements. the fifo logic manages frame retransmission for early collision conditions or discards the frame if late collision occurs. it also follows the truncated binary exponential backoff algorithm, collision and jamming procedures. the transmit fifo buffers the packets available for transmission in the main memory queues. if the transmit fifo gets empty before the packet currently in transmission reaches its end, an underrun condition is generated. when the switch core transfers the rest of the packet into the fifo the transmit mac safely discards it without affecting the next packet. underrun conditions will not occur if the system is operated at the recommended clock frequency or higher. for full duplex mode the TC6216M implements the flow-control algorithm according with the ieee 802.3x standard. the chip uses the xon/xoff method adjusting the pause value field inside the mac pause frame according to traffic conditions. the full duplex flow control can be enabled/disabled depending on autonegotiation result, pin configuration and/or eeprom settings. the TC6216M executes backpressure algorithm as half duplex flow control mode if not disabled by disbpr pin or eeprom (configregpx[1]) . the backpressure algorithm is based on carrier sense forced collisions and an aggressive backoff algorithm. the forced consecutive collisions generated for flow control purposes can be
TC6216M - 13 - ver. 2.1 5/24/01 limited to a maximum of 30 collisions if this option is selected. the default number of consecutive collisions can be changed by eeprom settings. this feature can be used to avoid hub partitioning. mac block diagram 8 traffic priority TC6216M supports advanced traffic priority features (qos). it provides three levels of priority: normal, high and very high priority. each class of priority has its dedicated queue for each transmission port. packets in priority mode (high or very high priority) will arrive sooner at the destination mac address. when all (3) priority queues for the same port are not empty the transmission bandwidth is used around 8% for the low priority queue, 30% for high priority and 62% for very high priority queue. the bandwidth distribution when one of the queues is empty can be observed in the table below: transmission bandwidth utilization factor priority queues if empty normal (low) priority high priority very high priority normal x 33% 66% high 11% x 89% very high 20% 80% x none 8% 30% 62% these priority rules apply for all ports and are independent of the port s speed mode or duplex mode. a special packet dropping mechanism is also implemented to offer more protection against overflow conditions for priority packets. if the packet memory load is exceeding an overflow threshold then all normal priority packets will be dropped on source port basis in order to save space for the priority packets. this will minimize the probability of packet loss in priority flows for senders that are not flow-control capable. rx fifo rx mac tx mac flow control tx fifo fifo control logic system interface mac rmii phy layer rm i i rx d a ta ( 2) tx d a ta (64) fc i nse r t ti me val ue ( 16) rx d ata (64) rm i i t x d a ta (2 ) fifo control logic
TC6216M - 14 - ver. 2.1 5/24/01 the qos mechanism supports multiple prioritization sources. packet priority can be checked via 802.1q vlan tag header tci bits (layer 2) and/or ip header tos bits (layer 3). if the value of tci/tos bits is ?0?, this packet will be treated as normal priority, if ?1? then it will be high priority, if more than ?1? then it will be very high priority. port based prioritization is also available. using port based priority the user can assign different priorities for each port. if vlan and ip priority are disabled or not labeled, all packets received on the same port will be forwarded with the corresponding assigned port base priority. when more than one prioritization methods are active at the same time (vlan, ip and/or port based) the priority resolution consists of maximizing the priority class. the qos can be configured using both pin configuration interface and/or eeprom settings. the vlan prioritization can be enabled by envlpr pin or by priorityreg[0] eeprom bit, while enippr pin or priorityreg[1] eeprom bit can be used to enable the ip priority. port based prioritization is available using prtpri(x) and prilev(x) pins for port 4 to 11, or equivalent eeprom bits configregpx[3] and configregpx[2] for each ports. setting prtpri(x) pin to 1 will configure the corresponding port in priority mode. prilev(x) pin selects between high ( 0 ) and very high priority ( 1 ). 9 trunk configuration TC6216M can setup two port aggregation links, named trunk a respectively trunk b , of up to 4 ports each. using this feature multiple TC6216M can be cascaded or interconnected with other switches supporting the trunking feature. the trunks can be independently configured according with tables below using pin configuration tnka0 , tnka1 respectively tnkb0 ,tnkb1 or using eeprom configuration (trunkcfgreg) . tnka1 tnka0 ports grouped within trunk a 0 0 trunk a disabled 0 1 trunk a groups ports 0 and 1 1 0 trunk a groups ports 0,1and 2 1 1 trunk a groups ports 0,1,2 and 3 tnkb1 tnkb0 ports grouped within trunk b 0 0 trunk b disabled 0 1 trunk b groups ports 14 and 15 1 0 trunk b groups ports 13,14 and 15 1 1 trunk b groups ports 12,13,14 and 15 the traffic on the ports of the same trunk will be automatically balanced. TC6216M can be selected from three balancing methods based on source port, sa and da as shown in the table below. they are selectable from tnkmod(0-1) pins or from eeprom trunkcfgreg register: tnkmod1 tnkmod0 method description 0 0 method 1. based on source port. 0 1 method 2. based on sa. 1 0 method 3. based on sa and da. 1 1 not used different stations connected on the same port may not send traffic on the same trunk line. the packet order is guaranteed for method 1 and 2 for unicast and broadcast packets. the packet order is guaranteed for method 3 only for unicast packets. the default mode for all trunking ports is 100mbps full duplex. tr unk port modes can be changed using eeprom settings although this is not recommended. also it is recommended for trunk ports to be interconnected with 100mbps full duplex capable ports only. if the user selects a trunk configuration it must
TC6216M - 15 - ver. 2.1 5/24/01 make sure that all ports are connected within the trunk, the port order is not mandatory. if one wire from a defined trunk is not connected, the trunk may not work properly. 10 flow control TC6216M executes backpressure for half duplex and is ieee 802.3x compliant for full duplex flow control operation. the chip uses xon/xoff flow control method in full duplex mode. for full duplex operation, if no eeprom is used and fcopt pin is asserted the autonegotiation flow control capability resolution is executed. this means that if bit 10 from the link partner advertisement register is not set then the transmission of flow control packets is disabled. if fcopt is 0 then the entire flow control operation for full duplex is always executed. the flow control on the receive side is always operational disregarding the state of fcopt pin. fcopt pin represents a global setting for all 16 ports. when the eeprom is used, the fcopt can be override by its equivalent bit flowcontrolreg[0]. supplementary a setting is offered per port basis dsfuldpxfc (configregpx[4]). setting this bit to 1 will disable the flow control on that port no matter of autonegotiation result. without eeprom fcopt pin a-neg (bit 10 from the phy's link partner register) fc ? ability 0 don t care enabled disabled disabled 1 enabled enabled with eeprom fcopt bit (flowcontrolreg) dsfuldpxfc bit (configregp x ) a-neg (bit 10 from the phy's link partner register) fc ? ability/port 1 disabled 0 0 don t care enabled 1 don t care disabled disabled disabled 1 0 enabled enabled the backpressure operation can also be disabled using disbpr pin or per port base using eeprom (configregpx[1]). in case a hub with many workstations is connected to a port, the hub may be partitioned in heavy traffic when the switch executes too musch continuous backpressure. TC6216M can prevent this when fullbp pin is not asserted by discontinuing the backpressure process after a determined number of consecutive collisions is reached. this number can be specified using flowcontrolreg, field backprlv. 11 broadcast in case of excessive broadcast the traffic can be throttled on source port basis. TC6216M implements an evolved throttling method based on both port bandwidth and broadcast memory utilization. this feature is enabled using bcsttr configuration pin or the eeprom broadcastreg[2] bit. the memory used at any time by broadcast packets that are received from the same port can not exceed a preset amount. this is represented by a number of 256 byte packet buffers that can be set using broadcastreg eeprom register, field memthrotreg. when no eeprom is present the default value of 8 buffers is used. when more than this number of buffers are in use by broadcast packets, any other broadcast incoming from the respective port will be dropped.
TC6216M - 16 - ver. 2.1 5/24/01 the broadcast receive bandwidth per port can be reduced to a value between 1.5% to 22% of the port s maximum bandwidth. when the broadcast bandwidth exceeds the preset value some broadcast packets will be dropped. the throttling bandwidth can be adjusted using register broadcastreg, field bndwthrotreg. it is obtained by multiplying the value in this field with 1.5%. the default value is 4 (6%). supplementary, but not depending of the broadcast throttling configuration, all broadcast packets will be dropped when the total amount of the memory used by broadcast packets exceeds a preset threshold. this situation will occur only when flow control for broadcast is disabled, otherwise no broadcast packet will be lost. the flow control for broadcast traffic can be enabled using fcbcsten pin or eeprom (broadcastreg[1]). even when broadcast flow control is disabled TC6216M is capable of taking continuos broadcast packets from one port and deliver them to all the other ports at maximum speed without losing packets. when TC6216M is configured in broadcastall mode all broadcast packets will be sent to all ports. if broadcastall mode is disabled the broadcast packets will be sent only to ports that have the link status on. link status is monitored by the phy polling entity that also reads the port mode autonegotiation result. 12 auto negotiation in auto-negotiation mode (assumed by default when the eeprom is not present) TC6216M is polling the phy s rmii management registers using the mdio line in order to extract the autonegotiated port mode information, full duplex flow control ability and the link status. the switch detects and follows any changes in less than 2 seconds. after reset TC6216M advertises the full duplex flow control capability (writing 1 to bit 10 from phy s advertisement register) and restarts the autonegotiation. if the port mode (speed and duplex) is forced by eeprom settings then this mode is also advertised before restarting the autonegotiation. in this case TC6216M will not advertise any other speed or duplex capability other than what is set by eeprom. port mode can be forced using configregpx bits 5 ? 7. 13 eeprom interface TC6216M can be configured using a serial eeprom device type at24c02a (2048 bits organized as 256 pages of 1 byte each). with this device the manufacturer can deliver a pre-configured system to their customers while the customers can reconfigure the system and retain their preferences. the TC6216M is able to operate without eeprom and can make effective use of its features using only the pin configuration interface. the eeprom configuration provides additional features and it can override all pin interface settings offering a jumperless configuration mode. for this reason, equivalent eeprom settings can be found for every configuration pin. a validation bit is provided for each one of the eeprom configuration registers. a dedicated validation register is reserved for this purpose and corresponding bits from this register must be set in order to enable the desired eeprom configurations. the eeprom configuration information is accessed by the TC6216M after each reset procedure. 14 programming the eeprom for configuration if the reset pin is hold low, the TC6216M s eeprom interface will go into high impedance state. this feature enables easy programming of the eeprom during installation or configuration. the eeprom can be programmed using an external parallel port. a dedicated signal from this port can be used to hold the reset pin low. once the TC6216M interface pins have got to the high impedance state the eeprom can be programmed by the parallel port through the sda and scl pins. to enable the at24c02a device to be accessed by the TC6216M, its page address input pins must be hardwired to 0 .
TC6216M - 17 - ver. 2.1 5/24/01
15 eeprom address map eeprom physical address bits register name validation bit description 00 [7:0] validreg [ 23 downto 16 ] - validate registers 01 [7:0] validreg [ 15 downto 8 ] - validate registers 02 [7:0] validreg [ 7 downto 0 ] - validate registers 03 [7:0] configregp0 [ 7 downto 0 ] validreg [ 0 ] port 0 configuration register 04 [7:0] configregp1 [ 7 downto 0 ] validreg [ 1 ] port 1 configuration register 05 [7:0] configregp2 [ 7 downto 0 ] validreg [ 2 ] port 2 configuration register 06 [7:0] configregp3 [ 7 downto 0 ] validreg [ 3 ] port 3 configuration register 07 [7:0] configregp4 [ 7 downto 0 ] validreg [ 4 ] port 4 configuration register 08 [7:0] configregp5 [ 7 downto 0 ] validreg [ 5 ] port 5 configuration register 09 [7:0] configregp6 [ 7 downto 0 ] validreg [ 6 ] port 6 configuration register 0a [7:0] configregp7 [ 7 downto 0 ] validreg [ 7 ] port 7 configuration register 0b [7:0] configregp8 [ 7 downto 0 ] validreg [ 8 ] port 8 configuration register 0c [7:0] configregp9 [ 7 downto 0 ] validreg [ 9 ] port 9 configuration register 0d [7:0] configregp10 [ 7 downto 0 ] validreg [ 10 ] port 10 configuration register 0e [7:0] configregp11 [ 7 downto 0 ] validreg [ 11 ] port 11 configuration register 0f [7:0] configregp12 [ 7 downto 0 ] validreg [ 12 ] port 12 configuration register 10 [7:0] configregp13 [ 7 downto 0 ] validreg [ 13 ] port 13 configuration register 11 [7:0] configregp14 [ 7 downto 0 ] validreg [ 14 ] port 14 configuration register 12 [7:0] configregp15 [ 7 downto 0 ] validreg [ 15 ] port 15 configuration register 13 [7:0] fcpauseval [ 15 downto 8 ] validreg [ 16 ] flow control pause value 14 [7:0] fcpauseval [ 7 downto 0 ] validreg [ 16 ] flow control pause value 15 [7:0] maccfgreg [ 7 downto 0 ] validreg [ 17 ] mac configuration register 16 [7:0] flowcontrolreg [9 downto 8] validreg [ 18 ] flow control register high 17 [7:0] flowcontrolreg [7 downto 0] validreg [ 18 ] flow control register low 18 [7:0] trunkcfgreg [ 7 downto 0 ] validreg [ 19 ] trunk configuration register 19 [7:0] broadcastreg [ 11 downto 8 ] validreg [ 20 ] broadcast configuration register high 1a [7:0] broadcastreg [ 7 downto 0 ] validreg [ 20 ] broadcast configuration register
TC6216M - 18 - ver. 2.1 5/24/01 eeprom physical address bits register name validation bit description low 1b [7:0] priorityreg [ 15 downto 8 ] validreg [ 21 ] reserved 1c [7:0] priorityreg [ 7 downto 0 ] validreg [ 21 ] priority register low 16 register description validation register - address: 00h-02h 23 0 validreg bit(s) field dscription 23 ?22 not used 21 ? 0 validreg eeprom configuration validation register validreg ? each bit from this field corresponds to an eeprom configuration register. configurations made using any of the eeprom registers will be in force only if the register is validated by setting to 1 the corresponding bit in this register. validreg [ 0 ] ? validation bit for configregp0 register validreg [ 1 ] ? validation bit for configregp1 register validreg [ 2 ] ? validation bit for configregp2 register validreg [ 3 ] ? validation bit for configregp3 register validreg [ 4 ] ? validation bit for configregp4 register validreg [ 5 ] ? validation bit for configregp5 register validreg [ 6 ] ? validation bit for configregp6 register validreg [ 7 ] ? validation bit for configregp7 register validreg [ 8 ] ? validation bit for configregp8 register validreg [ 9 ] ? validation bit for configregp9 register validreg [ 10 ] ? validation bit for configregp10 register validreg [ 11 ] ? validation bit for configregp11 register validreg [ 12 ] ? validation bit for configregp12 register validreg [ 13] ? validation bit for configregp13 register validreg [ 14 ] ? validation bit for configregp14 register validreg [ 15 ] ? validation bit for configregp15 register validreg [ 16 ] ? validation bit for fcpauseval register validreg [ 17 ] ? validation bit for maccfgreg register validreg [ 18 ] ? validation bit for flowcontrolreg register validreg [ 19 ] ? validation bit for trunkcfgreg register validreg [ 20 ] ? validation bit for broadcastreg register validreg [ 21 ] ? validation bit for priorityreg register port x configuration register - address: 03h-12h - note: x = 0 to 15
TC6216M - 19 - ver. 2.1 5/24/01 0 1 2 3 4 5 6 7 mo d e dup l ex
s pee d prtpr i dsfu l dpxfc pr i lev disbackpr not use d bit(s) field description 7 mode select source 6 duplex full / half duplex configuration 5 speed 100 mbps / 10mbps configuration 4 dsfuldpxfc disable full duplex flow control 3 prtpri port priority 2 prilev priority level 1 enbackpr enable backpressure 0 not used mode ? this bit selects the source of port mode configuration: mode duplex speed 0 auto ? negotiation auto ? negotiation 1 eeprom configuration eeprom configuration duplex ? if mode configuration is 1 this bit will set the port s duplex mode. when high the port will be set in full duplex, when low it is half duplex. speed ? if mode configuration is 1 this bit will set the port s speed mode. when high the port s data rate is 100mbps, when low it is 10mbps. dsfuldpxfc ? setting this bit to 1 will disable transmit full duplex flow control for port x . - default 0 portpriority ? when set forces port x in priority mode, otherwise the port will have normal priority. prioritylevel ? if the corresponding port is in priority mode then the port will have a very high priority rate if this bit is asserted, otherwise only high priority rate. flow control pause value - address: 14h-13h 15 14 10 11 12 13 0 1 2 3 4 5 6 7 8 9 fcpauseval bit(s) field description 15 ? 0 fcpauseval flow control pause value
TC6216M - 20 - ver. 2.1 5/24/01 fcpauseval ? 16-bits of data used by every port to determine backpressure duration after a flow control xoff condition occurs. this value does not need to be adjusted by user. - default 0000100000000000 = 2048 mac configuration register - address: 15h 0 1 2 3 4 5 6 7

bit(s) field description 7 fwdbcrc forward bad crc packets 6 rejmactype reject mac control type frames 5 phyaddr16 mdio phy address 16 to 31 4 ? 0 ifgconfig interframe gap configuration fwdbcrc ? when set to 1 the switch will not filter bad crc frames with valid sizes. this kind of frames will be forwarded as they were received (without correcting the crc). - default 0 phyaddr16 ? setting this bit to 1 will program the phy polling entity to use device address range 16 to 31 instead of range 0 to 15. - default 0 rejmactype ? when asserted the switch filters all mac control type frames (type 8808). ifgconfig ? these bits are used to set the minimum ifg. if default value is set then the ifg will have the standard minimum value of 960 ns, otherwise for one unit added the minimum ifg will be increased with 40 ns. - default 10101 = 21 flow control register - address: 17h-16h 15 14 10 11 12 13 0 1 2 3 4 5 6 7 8 9 flowcontrolreg not used backprlv fullbp disbpbk fcopt fairbackoff bit(s) field description
TC6216M - 21 - ver. 2.1 5/24/01 15 ? 10 not used 9 fairbackoff fair back off 8 disbpbk disable backoff in backpressure 7 ? 2 backprlv backpressure level 1 fullbp full backpressure 0 fcopt optional flow control fairbkoff ? selects the backoff mode. when 1 the standard backoff process is changed by resetting the collision counter after valid packet is received, instead of resetting after successful transmission. when 0 the standard backoff process is executed. - default 0 disbpbk ? if set to 1 then no backoff will be executed when a half duplex port is in flow control mode. when 0 , an aggressive backoff will be executed (recommended). fullbp ? when set to 1 the backpressure operation will be executed for a number of slot times determined by flow control pause value setting or until an xon command is received. when 0 the backpressure will be also stopped after reaching a number of consecutive collisions specified using backprlv field. backprlv ? specifies the number of consecutive collisions that will determine TC6216M to cancel the backpressure (see the setting above). - default 011110 = 30 fcopt ? when is set the full duplex flow control resolution will be executed. this means that if the link partner does not advertise the flow control capability, the switch will not execute the flow control on transmission side. as result no flow control pause frame will be generated, but transmission will be stopped if a valid flow control frame is received). if fcopt is not set then the full duplex flow control will always be in effect unless deactivated by configregpx[4] (dsfuldpxfc) . trunkcfgreg - address: 18h 0 1 2 3 4 5 6 7 tnka0 tnka1 tnkb0 tnkb1 tnkmod not used
this register provides eeprom equivalents for tnka[0-1], tnkb[0-1] and tnkmod[0-1] configuration pins. the trunks of TC6216M can be configured according with tables below: tnka1 tnka0 trunk ?a? ports 0 0 trunk a disabled 0 1 0 , 1 1 0 0, 1, 2 1 1 0, 1, 2, 3 tnkb1 tnkb0 trunk ?b? ports 0 0 trunk b disabled 0 1 14, 15 1 0 13, 14, 15
TC6216M - 22 - ver. 2.1 5/24/01 1 1 12, 13, 14, 15 tnkmod ? trunk balance mode select: tnkmod (1) tnkmod (1) descriptions 0 0 transmission port inside a trunk is selected using only the source port. 0 1 transmission port is selected using da. 1 0 transmission port is selected using both sa and da. 1 1 not used broadcast register - address: 1ah-19h bcsttr memthrotreg not used bcstall fcbcsten bndwthrotreg 15 14 10 11 12 13 0 1 2 3 4 5 6 7 8 9 broadcastreg not used bit(s) field description 15-12 not used 11-8 bndwthrotreg broadcast throttling bandwidth 7 not used 6-3 memthrotreg max broadcast memory load 2 bcsttr enable broadcast drop 1 fcbcsten flow control broadcast enable 0 bcstall broadcast all fcbcsten ? when set enables flow control operation for broadcast packets, otherwise broadcast will be dropped on queue overflow condition (throttling). bcstall ? when set all the broadcast packets will be sent to all ports. when cleared all broadcast packets will be sent only to active ports. the port activity is detected by monitoring the transceiver s link status. bcsttr ? when is set the broadcast traffic will be throttled on the receive port basis. memthrotreg ? when the bcsttr bit is set and all broadcast packets received on a single port and still waiting to be transmitted use a number of packet buffers that is greater than the number specified in this field, then any other broadcast incoming from this port will be dropped. - default 1000 bndwthrotreg ? the value contained in this field multiplied with 1.5% represents the percentage of the maximum bandwidth available for broadcast. if received broadcast on a port exceeds this bandwidth it will be throttled. - default 0100 priority register
TC6216M - 23 - ver. 2.1 5/24/01 - address: 1ch-1bh 15 14 10 11 12 13 0 1 2 3 4 5 6 7 8 9 priorityreg envlpr enippr reserved not used reserved not used reserved bit(s) field description 15-12 not used 11-8 reserved 7 not used 6-3 reserved 2 reserved should be 0 1 enippr enable ip priority 0 envlpr enable vlan priority enippr ? when asserted qos resolution will consider tos precedence bits from ip header. envlpr ? when asserted qos resolution will consider user_priority bits (tci field) from 802.1q vlan tag header. 17 timing requirements ? rmii receive timing requirements symbol description min. typ. max unit t refclk reference clock period - 20 - ns t srx crsdv, rxd to refclk rising setup time 0 - - ns t hrx crsdv, rxd to refclk rising hold time 4 - - ns refclk crsdv rxd t srx t hrx t refcl k rmii receive ? rmii transmit timing
TC6216M - 24 - ver. 2.1 5/24/01 symbol description min. typ. max unit t refclk reference clock period - 20 - ns t stx txen, txd to refclk rising setup time 5 - - ns t htx txen, txd to refclk rising hold time 4 - - ns refclk txe n txd t stx t htx rmii transmit ? phy management (mdio) timing symbol description min. typ. max unit t ch mdck high time - 15 * t refck *1 = 300 - ns t cl mdck low time - 15 * t refck *1 = 300 - ns t cm mdck period - 30 * t refck *1 = 600 - ns t md mdio output delay - 20 ns t ms mdio setup time 10 ns t mh mdio hold time 10 ns note: *1 t refck is the period of the rmii reference clock. t cl t ch t cm t md mdclk mdio mdio read cycle
TC6216M - 25 - ver. 2.1 5/24/01 mdio write cycle ? eeprom timing symbol description min. typ. max unit f scl scl frequency - f refck /1024=4 8.8 *1 - khz t low clock pulse width low 10 - - us t high clock pulse width high 10 - - us t buf time the bus must be free before starting a new transmission 5 - - us t hd.sta start hold time 5 - - us t su.sta start setup time 5 - - us t hd.dat data hold time 5 - - us t su.dat data setup time 5 - - us t su.sto stop set-up time 5 - - us t aa clock low to data out valid - - 4.9 us t dh data out hold time 0 - - us note: *1 f refck is the frequency of the rmii reference clock. scl sda (output) sda (input) valid t low t high t su.sta t hd.sta t buf eeprom interface timing t hd.dat t su.dat t su.sto t aa t dh valid valid valid
TC6216M - 26 - ver. 2.1 5/24/01 18 electrical specifications ? absolute maximum ratings permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the recommended operating conditions section. exposure to the absolute maximum conditions for extended periods may affect device reliability. parameter symbol min. max. unit i/o v ddi/o v ssi/o *1 ? 0.5 4.6 v supply voltage core v ddcore v sscore *1 ? 0.5 2.5 v input voltage v i v ssi/o *1 ? 0.5 6 v output voltage v o v ssi/o *1 ? 0.5 4.6 v storage temperature t stg -65 +150 c operation temperature t opt 0 70 c latch-up current i latch >200 ma note: *1 v ssi/o ,v sscore = 0v note: the maximum ratings are the limit value that must never be exceeded even for short time. ? recommended operating conditions the recommended operating conditions represents recommended values that assure normal logic operation. as long as the device is used within the recommended operating conditions, the electrical characteristics (dc and ac characteristics) are guaranteed. parameter symbol min. typ. max. unit i/o v ddi/o 3.0 3.3 3.6 v supply voltage core v ddcore 1.62 1.8 1.98 v junction temperature t j 0 25 125 c low-level input voltage v il -0.5 1.0 v high-level input voltage v ih 2.3 5.5 v ? dc characteristics parameter symbol min. typ. max. unit output low voltage v ol 0.4 v output high voltage v oh 2.4 v all outputs except for leds 8.8 14.1 17.0 ma low level output current led outputs i ol 24.2 38.8 46.7 ma all outputs except for leds 12.8 25.7 40.0 ma high level output current led outputs i oh 38.2 76.9 119.9 ma input treshold point v t 1.46 1.60 1.76 v rmii/mii input (schmitt trig.) low to high treshold point *1 v t+ 1.66 1.75 1.79 v
TC6216M - 27 - ver. 2.1 5/24/01 rmii/mii input (schmitt trig.) high to low treshold point *1 v t- 0.93 1.01 1.06 v input leakage current (high and low) i i +/-10 +/-1000 na tri-state output leakage current (high and low) i oz +/-10 +/-1000 na pull-up resistor r pu 56 77 122 k ? pull-down resistor r pd 51 69 127 k ? note: *1 this reffers to all inputs described as r(mii) in the pin listing section. 19 mechanical specifications lead pitch 0.50 mm package width x package length 28 x 28 mm lead shape gullwing sealing method plastic mold 208-pin plastic qfp
TC6216M - 28 - ver. 2.1 5/24/01 notice information in this document is subject to change without notice. tmi reserves the rights to change its products at any time. therefore, the customer is cautioned to confirm with tmi regarding the latest released version before placing orders. tmi devices are not designed, intended, authorized, or warranted to be suitable for use in life-supporting applications.

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